Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers. Platform: |
Size: 5886 |
Author:宋昆仑 |
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Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers. Platform: |
Size: 3387 |
Author:宋昆仑 |
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Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers. Platform: |
Size: 3856 |
Author:宋昆仑 |
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Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers. Platform: |
Size: 4092 |
Author:宋昆仑 |
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Description: 用verilog语言实现的ARM7处理器的标准内核的源代码程序,nnARM, 具有很好的参考价值-using Verilog language of the standard ARM7 processor core source code procedures nnARM, who have a good reference value Platform: |
Size: 457920 |
Author:王晨语 |
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Description: verilog硬件描述语言编程规范，描述如何使你编写的代码的可读性更高，可用性更强，并且使你在编程过程中少犯一些低级错误。-Verilog hardware description language programming standard, and describe how you prepared to make the code more readable, more availability, and will enable you to the programming process less committed some minor errors. Platform: |
Size: 63680 |
Author:崔崔 |
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Description: ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code Platform: |
Size: 5756 |
Author:刘超 |
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Description: verilog standard
verilog standard
verilog standard
verilog standard
verilog standard
verilog standard-verilog standard Platform: |
Size: 115712 |
Author:yupeng |
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Description: The Verilog
¤
Hardware Description Language (HDL) is defined in this standard. Verilog
HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because
it is both machine readable and human readable, it supports the development, verification,
synthesis, and testing of hardware designs the communication of hardware design data and the
maintenance, modification, and procurement of hardware. The primary audiences for this standard
are the implementors of tools supporting the language and advanced users of the language.
Keywords:
computer, computer languages, digital systems, electronic systems, hardware, hardware
description languages, hardware design, HDL, PLI, programming language interface, Verilog
HDL, Verilog PLI, Verilog
¤-The Verilog
¤
Hardware Description Language (HDL) is defined in this standard. Verilog
HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because
it is both machine readable and human readable, it supports the development, verification,
synthesis, and testing of hardware designs the communication of hardware design data and the
maintenance, modification, and procurement of hardware. The primary audiences for this standard
are the implementors of tools supporting the language and advanced users of the language.
Keywords:
computer, computer languages, digital systems, electronic systems, hardware, hardware
description languages, hardware design, HDL, PLI, programming language interface, Verilog
HDL, Verilog PLI, Verilog
¤ Platform: |
Size: 2177024 |
Author:bkaraca |
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Description: Introduction
Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in
DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide
hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst
cycle.
This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design
to meet specific design requirements. This document provides information on how this design operates and shows
the user where changes can be made to support other functionality. Platform: |
Size: 8192 |
Author:Robuster
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Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。
SPI相关缩写
SS: Slave Select，选中从设备，片选。
CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性
CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位
SCK = SCLK = SCL = SPI的时钟（Serial Clock）
Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。
对于一个时钟周期内，有两个edge，分别称为：
Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候；
Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices.
SPI related abbreviations
SS: Slave Select, selected from the device, chip select.
CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity
CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase
SCK = SCLK = SCL = SPI clock (Serial, Clock)
Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge).
For a clock cycle, there are two edge, respectively:
Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1;
Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;) Platform: |
Size: 6144 |
Author:helimpopo
|
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Description: 设计兼容51的指令集的处理器架构
编写兼容51处理器的Verilog代码 仿真
验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU internal data path, and according to the data path and the timing of the functional modules, I design the CPU controller, thus completing the design of the CPU core. Writing the module code in Verilog language and running the lighting program on DE2, I validate and test the related functions and performance.) Platform: |
Size: 13230080 |
Author:PhoebeBNN
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Description: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.) Platform: |
Size: 2432000 |
Author:sisuozheweilai |
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Description: Serial link systems have gradually dominated over parallel link systems in modern
high-speed data link communications. The use of differential signal serial
communications prolongs the length of the data transmission channels, which parallel
communications can not match due to the signal degradation effects caused by, for
example, crosstalk among parallel link wires. In addition, the maximum tolerable skew
among the parallel link wires limits their maximum allowable data transmission speed.
This chapter provides an introduction to serial link systems and also gives an outline of
the thesis, which is devoted to the development of single chip, high-speed, serial link
communications techniques for multi-channel and multi-standard applications. Platform: |
Size: 23811196 |
Author:61219131@qq.com |
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